The present invention generally relates to printed circuit boards, and more particularly to multilayer printed circuit boards comprising a three-layer core having a dual blind via interlayer interconnection unit. The present invention also relates to methods for forming a three-layer core of a multilayer printed circuit board.
The present trend in the design and manufacture of printed circuit boards (PCBs) is towards decreased size, smaller hole or via diameter, and higher interconnection density. High interconnection densities require multilayer PCBs having more than one signal layer with numerous interconnections therebetween.
Each signal layer of prior art multilayer PCBs typically consists of a patterned conductive metal layer. Adjacent conductive layers are separated by an insulating material or dielectric layer comprising, for example, a polyimide or a resin which may be reinforced with glass fiber. Interconnections between the various conductive layers are provided by holes or vias that extend through the intervening dielectric layer, wherein the vias or holes are plated, filled, and/or plated over with conductive material. Such vias or holes may be through holes, blind vias, or buried vias. Through holes extend to all conductive layers of a multilayer assembly. In contrast, blind vias and buried vias pass through only part of a PCB—blind vias having one end of the via exposed, and buried vias having neither end of the via exposed. Thus, a blind via connects two or more layers of a PCB and starts on an outer layer, but does not pass completely through the PCB. A buried via connects two or more inner layers of a PCB but no outer layer.
Two-layer cores, which consist of a thin dielectric layer covered with copper foil, form the basic building block of prior art PCBs. Typically, the dielectric layer of a two-layer core is covered with copper foil on both sides. Multilayer PCBs of the prior art may be formed by laminating two or more two-layer cores. After patterning the copper foil of the signal layers, the layers are laminated using heat and pressure. Plated via holes for interlayer connection may be formed by drilling in the z-axis between layers, e.g., by laser drilling, followed by plating the hole. A blind via may be formed by drilling partly through one or more dielectric layers, followed by plating the hole, or by forming a plated through hole and then laminating an additional layer on one side thereof. A buried via may be formed by forming a blind via and laminating an additional layer on the exposed end of the blind via, or by providing a plated through hole and laminating an additional layer on each side of the plated through hole. Such procedures or processes are well known in the art.
As noted above, the standard building block of prior art PCBs is a core consisting of a two-layer dielectric carrier. Stacking a μvia on either side of such a carrier requires a solid target pad for laser ablating down to (or building up from with additive technology) the top of the carrier's buried via. This requires creating either a solid copper through via, or a via that is filled and plated over in the carrier. Creation of such vias becomes problematic as via size and dielectric thickness decrease. In order to form a large enough via in the carrier to drill and fill effectively, the minimum producible drill-to-adjacent-feature spacing cannot be maintained. Likewise, filling a through via on a thin carrier has limited producibility due to limitations of via fill and plating processes related to decreased carrier thickness. Also, restrictions on high aspect ratio of the filled hole effectively limit the thickness of the carrier's dielectric layer. However, in certain situations a thicker dielectric layer might be required, e.g., for impedance purposes, or for overall finished dimensions of the PCB. Furthermore, thin dielectric layers, which may be required to maintain a minimum aspect ratio for μvias formed therein, may lack the necessary dimensional stability for processing, e.g., filling a plated hole, which may result in destruction of the carrier.
In addition, filling a via of the prior art usually requires multiple plating cycles, and consequently may result in unacceptably thick total surface copper for etching fine features on a signal layer. Consequently, a significant portion of the total surface copper may have to be removed by mechanical means during processing according to the prior art.
FIG. 1A is a cross-sectional view of a copper clad dielectric layer 10 for processing into a conventional two-layer carrier for a PCB, according to the prior art. Copper clad dielectric layer 10 includes a first copper layer 20, a second copper layer 22, and a dielectric layer 24 disposed between first and second copper layers 20, 22. Dielectric layer 24 may comprise a dielectric material, such as a glass fiber reinforced resin, or a polyimide, and the like.
FIG. 1B is a cross-sectional view of a conventional carrier 10′ for a PCB in the form of a two-layer core, according to the prior art. Carrier 10′ has two metal layers, namely a first copper layer 20 and a second copper layer 22, as well as a dielectric layer 24 disposed between first and second copper layers 20, 22. Carrier 10′ includes a plated through hole 40 which has been filled and plated over. Plated through hole 40 extends from a first pad 30 within first copper layer 20 to a second pad 32 within second copper layer 22. Plated through hole 40 serves as a conducting interconnection-between first and second copper layers 20, 22. Such plated through holes are well known in the art. Regions of the prior art two-layer core that lack first and second copper layers 20, 22, e.g., due to etching thereof, are represented by reference numeral 26.
FIG. 1C is a cross-sectional view of a conventional carrier 10″ for a PCB in the form of a two-layer core, also according to the prior art. Carrier 10″ includes a dielectric layer 24 disposed between first and second copper layers 20, 22, essentially as described for FIG. 1B. FIG. 1C shows a blind via 40′ which has been filled and plated over. Blind via 40′ extends from a first pad 30 within first copper layer 20 to a second pad 32 within second copper layer 22. Blind via 40′ serves as a conducting interconnection between different layers of a multilayer PCB, e.g., between first and second copper layers 20, 22. Such blind vias are well known in the art. Regions of prior art carrier 10″ that lack first and second copper layers 20, 22, e.g., due to etching thereof, are represented by reference numeral 26.
As noted hereinabove, conventional two-layer cores of the prior art have a number of drawbacks and disadvantages. As an example, as hole size (e.g., via diameter) diminishes to accommodate higher interconnect densities, dielectric thickness must also decrease in order to maintain a certain minimum aspect ratio for the hole, since holes having aspect ratios below the producible minimum cannot be filled efficiently or reliably. Restrictions on dielectric thickness, in turn, are associated with a number of other disadvantages. However, dielectrics below a certain thickness cannot be processed reliably, leading to destruction of many incipient cores and poor processing efficiency. For example, increased dielectric thickness may be required for impedance purposes. Furthermore, a PCB having a relatively large overall dielectric thickness may offer advantages for providing connections thereto. In addition, increased overall dielectric thickness may allow for production of a PCB having a greater overall finished thickness, for example, to fit within a particular housing of an instrument, device, or appliance.
As can be seen, there is a need for a multilayer PCB having an interlayer interconnection unit, the formation of which requires only a single plating cycle. The use of only a single plating cycle can result in decreased thickness of total surface copper, thereby facilitating formation of fine features without the need for mechanical reduction of the surface copper layer. There is also a need for a dual via interlayer interconnection unit for a multilayer PCB, wherein the interconnection unit allows an overall increased aspect ratio, as compared with prior art plated through holes and vias. There is a further need for a PCB core or subassembly wherein the total thickness of the dielectric, at minimum hole and pad diameter, can be increased when greater dielectric thickness is required, for example, for impedance purposes or for overall finished thickness.